Edinburgh, Scotland - CriticalBlue has announced enhanced support for the MIPS32 architecture within CriticalBlue's Prism product. Software developers will now be able to analyze their existing software applications and quickly assess the tangible benefits of migrating to MIPS32 multithreaded and multicore devices.
This expansion of Prism capabilities enables MIPS Technologies to provide their customers with a system to demonstrate the differentiation of the MIPS32 architecture in the context of the customers' own software applications.
Prism is an Eclipse-based embedded multicore programming system that allows software engineers to realize the full potential of multicore processors without significant changes to their development flow. Prism analyzes the behavior of code running on hardware development boards, virtual machines or simulators. It allows engineers to take their existing sequential code, and before making any changes, explore and analyze opportunities for concurrency. Having identified the optimal parallelization strategies in this way, developers will implement parallel structures and use Prism again to verify efficient and thread-safe operations.
The new Prism capabilities for the MIPS32 architecture are being developed in two phases. The first phase, available today, is an instruction level Platform Support Package (PSP) for the MIPS32 architecture, which enables analysis of software applications running under Linux on either hardware development boards or virtual machines such as QEMU. End users are split in their preference for development boards and simulators for development, and therefore Prism supports both flows. MIPS developers will now be able to trace their existing software applications on a single core platform and then quickly analyze the potential benefits of migrating to a multicore architecture, all in the familiar Eclipse framework.
In the second phase, available at the end of April 2010, a Core level PSP for the MIPS32 architecture will bring an additional level of accuracy to software developers. Going beyond software mapping to multicore hardware, with this release users will be able to quantify the benefit of software migration to hardware multithreading available in certain MIPS cores, such as the MIPS32 34K and 1004K families. Users will be able to analyze data cache misses on a thread, function or source line level, resulting in the ability to see the impact of such cache misses on the overall concurrent schedule. All of this can be done on an existing unmodified software application running on a single core model or development board. The MIPS32 Core PSP is the first Core level PSP to support hardware multithreading impact analysis.
A 30 day evaluation copy of the Instruction PSP for Prism for all 32-bit MIPS cores can be downloaded from the CriticalBlue website. The Core PSP will also be available for evaluation when released.
Initial hardware development boards supported by the Prism MIPS32 PSPs are the Ubiquiti RouterStation Pro (MIPS32 24KcTM core) and the Sigma Vantage 8654 (MIPS32 24KEfTM core). A Prism demonstration will be available in the MIPS Technologies booth, number 2410, at the Embedded Systems Conference and Multicore Expo on April 27-29, 2010 in San Jose, California.
For more information visit www.criticalblue.com.