Lattice Semiconductor Corp. announced the availability of Service Pack 1 for Version 8.0 of its ispLEVER FPGA design tool suite. According to Lattice (Hillsboro, Ore.), Service Pack 1 is an important update for users of LatticeECP3 FPGAs.
Service Pack 1 updates the device values to production characterized silicon for the LatticeECP3-150EA device, Lattice said. With SP1, static timing analysis, timing simulation and power calculation will report results that more accurately reflect the behavior of the actual production device, according to the company. PCS/Serdes calibration settings used for the supported I/O protocols have been tuned to provide more robust behavior, Lattice said.
HDL generation of generic DDR interfaces from the IPexpress tool, first introduced in ispLEVER 8.0, has been enhanced to include two additional interfaces, resulting in more design and implementation flexibility, Lattice said. There is also additional flexibility in the choice of pins for generic DDR interfaces, the company said.
The ispLEVER design tool suite is the flagship design environment for the latest Lattice FPGA products. It provides a complete set of powerful tools for all design tasks, including project management, IP integration, design planning, place and route, in-system logic analysis and more. The ispLEVER tool suite is available for download, or on DVD for Windows, UNIX or Linux platforms. Synopsys' Synplify Pro advanced FPGA synthesis is included for all operating systems supported, and Aldec's Active-HDL Lattice Edition simulator is included for Windows.
The ispLEVER 8.0 Service Pack 1 tool suite for Windows, UNIX and Linux users is available immediately without charge for customers with active design tool maintenance contracts. Pricing for the full ispLEVER design tool suite starts at $1,295 for the Windows version.