PARIS Power-focused EDA startup Azuro Inc. (Santa Clara, Calif.) said its PowerCentric low power clock tree synthesis tool has been included in the second release of TSMC's Integrated Sign-off Flow (ISF) in 65nm.
TSMC explained that the ISF is an automated RTL to GDSII chip implementation flow that integrates its foundry technology files, pre-qualified library, IP, EDA tools and sign-off margin recommendations into a fully automated scripted production-quality flow.
With the second release of the ISF, TSMC claimed its customers are able to tapeout with PowerCentric using either a Cadence or a Synopsys based P&R flow and reduce clock power by 25 percent or more.
"Collaboration between EDA vendors and foundries is vital to continued growth and profitability of the chip design industry," stated Paul Cunningham, co-founder and CEO of Azuro. "With this second ISF release TSMC is dramatically reducing the cost and time to tapeout for large chip companies and small chip startups and they are doing this without any sacrifice in silicon quality. The seamless grab-it-and-go integration of PowerCentric into ISF while expanding its P&R tool support is a perfect example of the benefits of their ecosystem driven approach."
Azuro's PowerCentric is a clock tree synthesis tool for digital standard cell based chip designs. It is claimed to reduce chip power by up to 20 percent and to increase designer productivity on designs with complex clock networks.
Founded in 2002, Azuro is a privately held company with R&D offices in Cambridge, England.