Santa Clara, Calif.Tensilica Inc. has introduced its third generation ConnX 545CK 8-MAC (multiply-accumulate) VLIW (very long instruction word) DSP core for SoC designs.
Improvements in its third generation dataplane processor (DPU) core deliver up to 20 percent faster clock speed, 11 percent smaller die and up to 30 percent lower power consumption, according to Tensilica.
The ConnX 545CK is intended for SOC dataplane signal processing because it allows system control and high-speed signal processing throughput in a single core with a single compiler and single instruction stream. It combines a base CPU controller with a DSP that can sustain eight simultaneous MAC operations on independent data pairs per cycle, utilizing the 160-bit vector registers.
The ConnX 545CK features a 3-issue VLIW architecture with eight 16-bit multipliers that operate in SIMD (single instruction, multiple data) mode. The core can sustain eight parallel multiply-accumulate operations per cycle. The compiler automatically vectorizes code to take maximum advantage of the architecture. It also has two 128-bit load/store units and a built-in Viterbi convolutional coder accelerator.
One of the key features of the ConnX 545CK is the 32-bit input/output Queue interfaces that function like FIFOs (first in, first out), to bypass the system bus and communicate directly to streaming data interfaces. This allows much faster data throughput than traditional DSPs, which require memory-based load and store operations on each data element.
The ConnX 545CK Revision C is available now. In 65GP optimized for high speed, the ConnX 545CK delivers over 600 MHz operation.
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Tensilica Inc., www.tensilica.com