Akya Ltd. has enhanced its dynamically reconfigurable logic (DRL) IP. ART2.1 can now run up to twice as fast as its predecessor and is designed to work better with code generated by high-level-language compilers.
Akya (Selby, UK) launched its first generation, the ART2, in May 2009. The privately held group had been developing the 'ART' technology since 2005.
The company says its DRL technology has huge advantages over other programmable technologies in terms of power, speed and size, has a variety of applications in everything from portable media players to telecommunications backbones.
ART technology makes the design and implementation of reconfigurable chips simpler by separating dataflow circuitry from control logic, and by providing a large, ready-made library of IP building blocks for designers to work with.
It simplifies the process of designing dynamic circuitry with two high-level, custom-made design languages; one for data flow and one for control. Akya provides training in the simple-to-use ART2 architecture compiler (Artac), as well as comprehensive support, providing an easy route for training staff in the new languages.
Akya has introduced two main innovations to ART2.1. The first is a modified configuration instruction pathway, which allows up to 2x system clock speed compared to ART2.0. The second is an augmented interconnect sequencer instruction set, improving the performance of code generated by, for example, C compilers.
As part of its ongoing efforts to facilitate faster, simpler design of DRL chips Akya is even developing its own ‘ART2C’ C compiler. This is in recognition of the huge role C plays in modern system design, and the need to offer a level of abstraction equivalent to that available when designing traditional architecture.
With ART2.1 OEMs should be able to cheaply mass-produce a single core product, for example a media player semiconductor, and differentiate from product to product by adjusting the DRL element. Bug-fixes and updates can be fixed after tapeout, and even over-the-air, where appropriate.