NXP Semiconductors is developing two boards designed to demonstrate the interoperability of its CGV JESD204A-compliant high speed data converter family with Lattice Semiconductor's ECP3 FPGA family.
In February it announced that CGV series of data converters were interoperable with FPGAs from Altera and Xilinx.
The NXP CGV high speed data converters utilize an enhanced implementation of the JEDEC JESD204A standard serial interface to reduce the number of interconnect signals between data converters and VLSI logic devices.
One demo board (available now)features the NXP ADC1413D and the Lattice ECP3 device, while the other board features the NXP DAC1408D and the Lattice ECP3 device and will be available in September 2010.
The demo boards are USB powered, and can work together (with the DAC board output feeding the ADC board input) hosted by a single notebook computer with two spare USB ports running LabView or other signal analysis software.
CGV stand for Convertisseur Grande Vitesse and designates NXP's compliant, superset implementation of the JEDEC JESD204A interface standard, with a 28 percent increase in the transmitter rate (up to 4.0 Gbps versus the standard rate of 3.125 Gbps) and a 400 percent increase in the transmitter reach (up to 100 cm versus the standard reach of 20 cm).
The enhanced CGV features include multi device synchronization (MDS) for the DAC1408D series of D/A Converters. NXP has implemented this optional feature to enable LTE MIMO base station and other advanced multi-channel applications. NXP’s implementation of MDS enables up to sixteen DACs data streams to be sample synchronized and phase coherent.
The LatticeECP3 FPGA family offers multi-protocol 3.2G SERDES with XAUI jitter compliance, DDR3 memory interfaces, powerful DSP capabilities, high density on-chip memory and up to 149K LUTS, all with half the power consumption and half the price of competitive SERDES-capable FPGAs.