PARIS Power-focused EDA startup Azuro Inc. (Santa Clara, Calif.) has introduced version 5.2 of its PowerCentric clock tree synthesis tool for digital standard cell-based chip designs.
Azuro claimed that PowerCentric 5.2 deploys a proprietary new criticality-aware clustering algorithm to further reduce clock insertion delays by an average of 15 percent without any impact on clock power, area or skew. The tool also includes full support for version 1.1 of the Common Power Format (CPF).
“As our customers migrate to 40nm and 28nm, achieving the lowest possible insertion delays is becoming critical to manage timing closure in the backend of the design flow,” stated Paul Cunningham, CEO of Azuro.
He continued: “But the key challenge is how to achieve these insertion delays without an unacceptable impact on power. Criticality-aware clustering uniquely blends buffering for speed with buffering for power to achieve an average of 15 percent reduction in clock insertion delays while at the same time maintaining our core value proposition of reduced clock power.”
PowerCentric 5.2 is available now and in production use at several customers, the company concluded.
For additional information about PowerCentric, click here.