PARIS Power-focused EDA startup Azuro Inc. (Santa Clara, Calif.) claimed that the latest version of its Rubix clock concurrent optimization tool delivers a 15-percent increase in clock frequency.
Rubix is a clock concurrent optimization tool that is said to increase chip speed by up to 20 percent and accelerate chip time to market. Rubix fits seamlessly into a design flow using the same placed-gates to placed-gates flow integration interface as PowerCentric, the company's clock tree synthesis tool for digital standard cell-based chip designs.
Azuro said Rubix 1.4 deploys refinements to product’s underlying timing-driven placement, logic sizing, and useful skew-based clock tree synthesis algorithms, resulting in an average 15 percent increase in clock frequencies beyond traditional skew-balanced flows, 5 percent higher than the previous version of Rubix.
The product also includes full support for version 1.1 of the Common Power Format (CPF), Azuro noted.
For additional details on Rubix, click here.
Paul Cunningham, CEO of Azuro, commented: "At 40 and 28nm, building clocks to deliver the best timing rather than to be skew balanced is becoming a must-have to meet schedules and manage power consumption. With this new release of Rubix we are seeing yet further improvements in our already significant clock speed gains, even on high performance CPUs and GPUs. These improvements typically come with impressive 10 to 30-percent reductions in leakage power as well.”
In parallel, Azuro announced the availability of PowerCentric 5.2 clock tree synthesis tool.
Azuro claimed that version 5.2 of PowerCentric deploys a proprietary new clustering algorithm to further reduce clock insertion delays by an average of 15 percent without any impact on clock power, area or skew. The tool also includes full support for version 1.1 of the Common Power Format (CPF).