A high-definition (HD), surveillance internet protocol (IP) camera reference design on a single FPGA has been developed by Altera Inc. and features Cyclone III or Cyclone IV FPGAs and intellectual property from Eyelytics and Apical.
The design supports AltaSens' 1080p60 A3372E3-4T and Aptina's 720p60 MT9M033 HD wide dynamic range (WDR) CMOS image sensors. It is designed to provide surveillance equipment manufacturers with the ability to reduce board space, lower power consumption, increase flexibility and reduce development time compared to previous architectures using traditional digital signal processors and ASSPs.
Altera claims that traditional digital signal processors and ASSPs don't have the processing power required to accept the large bandwidth of data from 1080p and 720p WDR CMOS sensors (for instance, a full HD raster is 2200x1125 pixels x 16+ bits per pixel x 60 frames per second, resulting in >2 Gbps bandwidth).
The Cyclone series FPGAs can handle the large amounts of data generated by the latest HD WDR CMOS image sensors. In previous designs, HD WDR camera systems required FPGAs to perform the 'front end' data processing while a digital signal processor or an ASSP handled the 'back end' video encoding. These chips can be replaced by a single FPGA.
The HDsurveillance IP camera reference design includes Apical's ISP incorporating WDR processing 'iridix' together with advanced temporal and spatial noise reduction and Apical's 'checkerboard demosaic' core for the Altasens A3372E3-4T WDR mode.
3A functions, such as auto exposure and auto white balance are implemented in software on Altera's Nios II embedded soft core processor while Eyelytics' H.264 video encoder is capable of 720-line progressive 30 frames-per-second encoding or 1080-line progressive 15 frames-per-second encoding in main profile
Camera designers have to customize the FPGA with their own specific features, such as adding their own software for motion detection, and pan, tilt and zoom control.
More details and a video demo are available here.