PARIS EDA and IP company Dolphin Integration SA has introduced a panoply of silicon IPs optimized for high density so that designers can increase the density of their SoC by up to 10 percent.
Dolphin Integration (Meylan, France) claimed that the 65nm High Density Panoply represents a complete solution for the whole logic design to address the cost reduction challenge at the architectural level.
The panoply includes Single Port and Dual Port RAMs, metal programmable ROMs, Register Files and standard cells.
It is designed for consumer and industrial applications with high fabrication volumes and low cost manufacturing requirements, Dolphin Integration specified.
For additional details on Dolphin Integration's High Density Panoply, click here.