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Digital ADC IP uses digital library cells, benefits ASICs and FPGAs

7/20/2010 12:45 PM EDT
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Stellamar
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re: Digital ADC IP uses digital library cells, benefits ASICs and FPGAs
Stellamar   8/4/2010 8:37:06 PM
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Stellamar uses a revolutionary technology which allows us to achieve higher resolutions with lower clocks compared to designs based on Lattice’s technique. Stellamar Marketing

DrFPGA
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re: Digital ADC IP uses digital library cells, benefits ASICs and FPGAs
DrFPGA   7/24/2010 2:02:04 AM
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Wonder if this uses the technique described in a Lattice write-up: http://www.eetimes.com/design/analog-design/4008891/Leveraging-FPGA-and-CPLD-digital-logic-to-implement-analog-to-digital-converters

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