EDA and IP company Dolphin Integration SA now tackles the dynamic power consumption challenge at the architectural level with the introduction of a panoply of memories and standard cells that offer dual voltage capability for the 180nm process.
Because the increasing complexity of SoCs impacts the silicon area and power consumption, power management must be managed at the architectural level. Then, Dolphin Integration (Meylan, France) has launched a panoply of memories, standard cells and regulators that offer dual voltage capabilities and are delivered with characterizations for 1.8 V and 1.1 V in the 180 nm G process node.
Dolphin Integration said customers’ Benchmark results versus alternative solutions indicate that this Panoply enables dividing dynamic power consumption by up to 4 when operating at nominal voltage and by up to 7 when operating at low voltage.
Dolphin Integration said that the Ultra Low Power Panoply includes the Pluton architecture for Single Port RAM, the Mars architecture for Dual Port RAM, the patented Cassiopeia architecture for Metal programmable ROM, and the ultra high density standard cell library SESAME uHD-BTF DV.
For additional information on the Ultra Low Power Panoply, click here