Laguna Hills, Calif. - Novelics Corporation has expanded its portfolio with coolSRAM-6T embedded memory IP and MemQuest compiler, enhanced with Novelics 3G optimizations, and implemented in bulk logic CMOS technology. The new IP enables ASSP and ASIC designers to achieve higher performance and more power-efficient system-on-chips (SoCs) at no increase in manufacturing costs.
Novelics MemQuest compiler environment enables architectural analysis for access time, active power, leakage, and area. coolSRAM-6T IP includes an embedded grid-style power mesh . The power supply lines are available for user tapping, which are located on Metal 4 for best power integrity and simplest IR-drop analysis. This arrangement can support up to a 512 bit-wide bus to achieve great bandwidth and g up to 2 Mbits of block size.
For small geometries such as 40nm, power leakage constitutes a large portion of power consumption, forcing SOC designers to make a tradeoff between speed and design leakage. Novelics' coolSRAM-6T offers options to use standard Vt (SVT) transistors or High Vt (HVT) transistors to achieve the best tradeoffs between speed and leakage. For further reduction of leakage, Novelics’s advanced source biasing technique is complemented with advanced power gating techniques. Three easy to use power modes are offered: a low leakage active mode when an operation is performed; a lower leakage standby mode where data is retained but no operations can be performed; and a sleep mode where leakage is minimized and data is destroyed.
Novelics has minimized memory latency and maximized speed by application of high speed/low power decode logic and implementation of ultra-fast output circuit paths. Novelics' edged-based clocking scheme enables designers to achieve the best speed with no restriction on clock duty cycle.
Other application-specific options such as row and column redundancy, ECC, MUX for BIST and DFT scan, are also offered to achieve optimum yield.
“Embedded memory typically represents 30-60 percent of the transistors on a SOC chip and is growing, and therefore plays a crucial role in a designer’s ability to differentiate their designs with the shortest design cycle” said Farzad Zarrinfar, president and CEO at Novelics. “Novelics is expanding its portfolio beyond existing 180nm-55nm offering with our coolSRAM-6T in leading 40nm process technologies with optimum active power consumption, leakage, speed, area, and block resolution. This will enable customers to differentiate themselves in markets such as wireless communication, video, portable multimedia, smart grid, storage, image processing, and connected home entertainment.”
Novelics customers have reported comprehensive benefits from Novelics memory IPs. For various configurations, customers have achieved 10 percent higher speed. The same configurations are available with area savings up to 7 percent and 7 percent less dynamic power consumption than competitors.
Novelics memory IPs are implemented for standard logic CMOS processes with no additional masks to minimize cost and maximize reliability and portability. We enable chip designers to achieve differentiated ICs, translating into electronic devices that are less expensive, physically smaller, run cooler, have longer battery life and lighter weight.
The SRAM-6T in 40nm is available for licensing now. The initial offering is in TSMC’s 40nm GP/LP technologies. Support for UMC, GF, and SMIC will also be offered.
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