Oasys Design Systems said it has added SystemVerilog support to RealTime Designer, a design tool for physical RTL synthesis of 100-million-gate designs.
Support for SystemVerilog comes standard with RealTime Designer and is available immediately. In addition to SystemVerilog, RealTime Designer accepts Verilog and VHDL input, along with standard timing and physical libraries, SDC timing constraints and floorplans.
Launched a year ago, RealTime Designer is capable of synthesizing RTL to placed gates in a single pass and in a fraction of the time compared to traditional synthesis, according to Oasys.
The Santa Clara-based company claimed that traditional logic synthesis is running out of steam on designs of 20 million gates or larger. Synthesis is done a block at a time and without the context of the chip's floorplan. This approach typically leads to numerous iterations between synthesis and layout and suboptimal results in layout, according to Oasys.
RealTime Designer follows a "Place First" methodology that takes the RTL, partitions it into blocks, places the RTL in the context of a floorplan and implements each block all the way to placement.
Chip-level constraints are automatically propagated across the blocks and the design is optimized by repartitioning it at the RTL and re-implementing until the chip-level constraints are met.