Synopsys Inc. has presented the HSPICE Precision Parallel (HPP)
multi-threading technology that is claimed to deliver up to 7X
simulation speed-up for complex analog and mixed-signal designs.
HSPICE Precision Parallel technology, coupled with enhanced convergence algorithms, advanced analog analysis features and foundry-qualified process design kits, extends HSPICE for verification of complex analog and mixed-signal designs. Its scalable algorithm delivers up to 7X speed-up on 8-core CPUs while maintaining golden HSPICE accuracy, according to the company.
HPP combines an adaptive sub-matrix technology with optimized cache utilization and streamlined device model evaluation to obtain fast, highly-scalable performance on todayís multicore machines. Efficient memory management allows simulation of post-layout circuits larger than 10 million elements.
Synopsys specified that HSPICE Precision Parallel technology is in limited customer availability. It is expected to be generally available in December.
Besides the HPP technology, Synopsys said the HSPICE 2010 solution includes enhanced convergence algorithms, advanced analog analysis features and foundry-qualified support for process design kits (PDKs) that extend HSPICE gold-standard accuracy to the verification of complex circuits such as phase-locked loops, SERDES, data converters, high-precision custom digital and power management. With HSPICE 2010, design teams can accelerate verification of their analog circuits across process variation corners and reduce the risk of silicon respins, the company concluded.
To view a video introducing HSPICE Precision Parallel Technology, click here