Dolphin Integration has launched the HD BIST (Built-In-Self-Test) as part of its High Density – Low Power Panoply of silicon IPs.
The increasing number of sRAM instances implies growing BIST costs: at chip level, the additional silicon area for the fabrication testing of the sRAMs may easily represent 5 to 10 percent of additional area. Dolphin Integration's HD BIST is 50 percent smaller than alternative solutions.
The HD BIST is a flexible test solution for ensuring high memory reliability. It performs: • Algorithm programmability • Test under actual conditions of use (frequency, voltage…) • To diagnose yield loss and define the appropriate corrective actions, the HD-BIST can be combined with Dolphin Integration’s BISD (Built-In Self Diagnostic)
The HD BIST can be used to help test engineers reduce time-to-market: • Quick fault detection thanks to parallel testing of several instances • True “Self-Test” resulting in a pass/fail indication • BIST solution optimized per instance
Eventually, Dolphin Integration has 2 testing solutions for industrial test used in fabrication: • The HD BIST (Built-In Self Test) will test the functionality of the memory during the fabrication of the SoC. With the HD BIST, SoC integrators will benefit from faster and cheaper manufacturing tests leading to a more competitive product. • The universal BISD (Built-In Self Diagnostic) allows to also test the functionality of the memory. Moreover, the universal BISD enables the SoC integrator to identify where the errors come from (process, design…). BISD helps diagnose yield loss and define the appropriate corrective actions.
For additional information about HD BIST, click here.
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