As part of a collaboration with the Common Platform Alliance (CPA), Mentor Graphics Corp. has designed a test chip using its netlist-to-GDSII solution for CPA 32nm and 28nm high-k metal gate (HKMG) IC manufacturing technologies.
Mentor said its solution aims to meet customers’ needs for early signoff quality manufacturing (DRC/DFM) closure, multi-mode multi-corner (MCMM) timing/SI closure, low power design and fast time to market. It includes the Olympus-SoC place and route system and the Calibre physical verification and DFM platform.
The Olympus-SoC physical design system provides native concurrent multi-corner multi-mode (MCMM) optimization, automation for all low power design methodologies, 100M+ gate capacity, and parallel timing engine to deliver efficient scaling on multicore, multiprocessor computing platforms. The Olympus-SoC router provides support for complex 32/28nm DRC/DFM rules and recommended rules for yield improvement at leading foundries.
Mentor's Open Router architecture enables native invocation of Calibre engines during design. Using this interface, the Calibre InRoute manufacturing closure solution provides sign-off quality checking and repair during physical design within the Olympus-SoC cockpit. The Calibre golden signoff platform provides automated antenna fixing, optimized wire spacing, redundant via insertion, smart metal fill, and ERC checking in addition to DRC and LVS.
The Common Platform was formed by IBM, Samsung Electronics and GlobalFoundries to accelerate the availability of leading-edge technology to foundry customers. The Alliance features 28-nm, 32-nm, 45-nm, 65-nm and 90-nm process technologies.
Join our online Radio Show on Friday 11th July starting at 2:00pm Eastern, when EETimes editor of all things fun and interesting, Max Maxfield, and embedded systems expert, Jack Ganssle, will debate as to just what is, and is not, and embedded system.