Synopsys Inc. has introduced the DesignWare DDR PHY compiler to facilitate the integration of memory interface IP.
The DesignWare DDR PHY compiler provides a web-based GUI to assemble a
customized, high performance DDR PHY for SoCs. The DesignWare DDR PHY
compiler assesses more than 60 variables and allows the evaluation of
unlimited ‘what if’ scenarios. The output of the PHY compiler is a
customized hard DDR PHY that is optimized for the target application.
Synopsys' DesignWare DDR PHY compiler supports the DesignWare
DDR2/3-Lite, DDR 3/2 and DDR multiPHY IP products. Its GUI guides
designers through a series of decisions as they construct their DDR PHY
from hard IP components, including application-specific DDR I/Os.
Designers have control over multiple variables including supported DRAM
types (such as DDR3, DDR2, Mobile DDR and/or LPDDR2), foundry and
process node, memory channel width, power-to-signal ratios, core power
requirements and other physical placement variables.
The DesignWare DDR PHY compiler produces an instantly viewable image of
the DDR PHY layout, a list of the pins, area, a power consumption
report, placement scripts and an RTL model of the PHY.
The DesignWare DDR PHY compiler is available to licensed customers of select DesignWare DDR PHY IP.
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