Synopsys Inc. has enhanced the architecture of its DesignWare Universal DDR Memory Controller to accelerate the access to off-chip DRAM and deliver higher throughput for SoC designs.
Synopsys' DesignWare Universal DDR Memory Controller now delivers up to 30 percent lower latency and up to 15 percent higher throughput than the previous generation controller.
Among the new features, Synopsys cited the high priority bypass and configurable 'look-ahead'.
- The high priority bypass option enables designers to improve latency by bypassing the scheduling algorithm, allowing immediate access to the DRAM.
- The configurable ‘look-ahead’ feature provides intelligent scheduling to maximize throughput by prioritizing out-of-order transactions to the DRAM, allowing designers to make trade-offs between area and performance.
In addition, the Memory Controller:
- Offers a DFI 2.1-compliant interface to the DDR PHY,
- Delivers memory system performance of up to 2133 Mbps,
- Supports the DDR3, DDR2, LPDDR and LPDDR2 SDRAM standards.
The DesignWare Universal DDR Memory Controller is part of Synopsys’ comprehensive DesignWare DDR IP offering that consists of digital controllers and PHY IP supporting DDR, DDR2, DDR3, LPDDR and LPDDR2. The DesignWare DDR IP supports leading 130 nm, 90 nm, 65 nm, 55 nm, 45/40 nm and 32/28 nm technologies.
The enhanced version of the DesignWare Universal DDR Memory Controller single-port configuration is expected to be available in March 2011.