Intersil Corporation has announced its newest family of analog-to-digital converters (ADCs); pin-compatible 12-, 14- and 16-bit ADCs with sample rates from 130 to 500 megasamples per second (MSPS). The entire family is claimed to provide a significant reduction in power consumption over competitive devices, consuming as little as one-third the power.
Target applications include power amplifier linearization, radar and satellite antenna array processing, broadband communications, high-performance data acquisition and communication test equipment.
The first device to be introduced is the ISLA214P50, a 14-bit, 500MSPS ADC that consumes 63 percent less power while sampling at a rate 25 percent higher than any other 14-bit ADC.
The ISLA214P50 was designed using Intersil's proprietary FemtoCharge technology and operates from a 1.8V power supply. The new converter's ultra-high sample rate and resolution improve sensitivity and accuracy, while the decrease in power consumption allows simplified thermal and power system design.
At a sample rate of 500MSPS, the ISLA214P50 features a signal-to-noise ratio (SNR) of 72.7dBFS with spurious free dynamic range (SFDR) of 84dBc for fIN = 30MHz (-1dBFS).
The ISLA214P50 was recently selected by Spectrum Signal Processing By Vecima, a leading provider of high-performance, software-reconfigurable signal processing platforms, for use in their RF-4902 Wideband Frequency-Agile RF Transceiver.
Because the ISLA214P50 consumes only 835mW of power, it can be used in systems that cannot tolerate the bulky heat sinks and fans that are needed to cool competitive devices. A serial peripheral interface (SPI) port provides access to the ADC's extensive feature set, such as power-management functions, output test pattern generation and output code format selection. Digital output data is presented in selectable LVDS or CMOS modes.
The ISLA214P50 uses two time-interleaved 250MSPS ADCs to achieve the resulting 500MSPS sampling rate. A single 500MHz conversion clock is presented to the converter, and all interleave clocking and correction is managed internally. The proprietary Intersil interleave engine optimizes performance using automatic fine correction of offset, gain and sample time mismatches between the unit ADCs.
The combination of FemtoCharge and I2E technology results in the industry's most power-efficient architecture for achieving extremely high sample rates without sacrificing dynamic performance.
Other members of the family will include single and dual 12-, 14-bit, and 16-bit ADCs, offering unparalleled dynamic performance and ultra-low power consumption. All single channel devices have been designed to be pin-compatible to facilitate design reuse and significantly reduce time-to-market.
Similarly, all dual channel devices are pin-compatible. All devices will be available in space-efficient 10x10mm, 72-pin QFN packages. For area-constrained PCBs, a subset will be offered in a 7x7mm, 48-pin QFN package, reducing the already small footprint by an additional 51 percent.
All family members include the ability to synchronize multiple ADCs, which, when combined with exceptional low power consumption and small physical size, make them ideal for multi-channel, highly parallel systems.
Courtesy of EE Times Europe