Oasys Design Systems Inc. has enhanced its Chip Synthesis platform, including chip-level power analysis and the ability to re-synthesize a design from the register transfer level (RTL) with new power constraints.
RealTime Designer, based on Oasys' Chip Synthesis technology, is the first design tool for physical RTL synthesis of 100-million gate designs. It allows power to be managed at the chip level and enables project teams re-synthesize an existing RTL design to take into account a new power architecture. It can read input files from the Common Power Format (CPF) from Si2, the way low-power policies are described, and will soon support IEEE Standard 1801-2009, based on Accellera’s Unified Power Format (UPF).
RealTime Designer is said to enable designers to experiment with voltage levels and power tradeoffs at the architectural level for maximum impact, while taking all power measurements from a fully placed netlist. During synthesis, RealTime Designer inserts all the appropriate level shifters, isolation cells and retention registers, as specified in the power policy.
No need to have a complete CPF or UPF file before using RealTime Designer. Oasys claimed that the power policy can be explored for various scenarios and RealTime Designer can be used interactively to consider alternative power policies without needing them to be fully specified in an external file. Once this “what-if” analysis is complete and the final policy has been selected, RealTime Designer writes out the CPF or UPF file to be used by other tools, such as analysis and verification, and traditional place and route tools.
The latest version RealTime Designer is shipping now.
It is priced from $395,000 for a one-year, time-based license.
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