DeFacTo Technologies S.A. announced PLX Technology has licensed its DeFacTo Technologies’ HiDFT-SIGNOFF Design for Test (DFT) solution.
HiDFT-SIGNOFF main features:
PLX Technology said its portfolio of high-end PCIe Switches, PCIe Bridges, NAS and DAS storage solutions, USB Controllers and other connectivity products will benefit from increased test coverage earlier in the design flow, without requiring additional engineering resources.
DeFacTo claimed its HiDFT-SIGNOFF solution allows scan logic insertion at RTL. HiDFT-SIGNOFF enables designers to create a high-level design for test signoff methodology, closing the gap between RTL and DFT. HiDFT-SIGNOFF allows early identification of test issues and enables new pre-synthesis design and DFT verifications.
. Enables testability signoff
. Testability DRC
. ATPG-aware Test Coverage Evaluation (TCE)
. Accuracy of Test Coverage Evaluation (TCE) within 0.5%
. AutoFix correction of scannability problems
. Pinpoints testability weaknesses (controllability/observability issues)
. Test point insertion for test coverage improvement
. Hierarchical scan insertion methodology using test models (CTL)
. Graphical interface to debug ATPG faults
. Allows new DFT verifications at RTL: test vectors simulation, test power analysis, etc...
To access DeFacTo Technologies' HiDFT-SIGNOFF datasheet here