Mentor Graphics Corp. has released its next-generation emulation platform to accelerate the verification of 100-Gigabit Ethernet products.
The platform, consisting of Mentor's Veloce family of emulation products and iSolve Ethernet Switch product, enables network equipment designers to test their complete system, including software and hardware, as well as employ real-world network traffic early in the development cycle.
When combined with the Veloce product family, the iSolve Ethernet Switch solution delivers a high-performance, large multi-port and easy-to-use system verification environment to develop new and innovative networking products without compromising delivery schedules.
The platform can be used with a traditional In-Circuit Emulation as well as a high-performance Transaction-Based Acceleration mode of operation.
The solution is available now for deployment at customer sites.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.