Mentor Graphics Corp. and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) announced they have collaborated to enrich TSMC's Reference Flow 11 low power verification solutions.
Mentor Graphics said it has expanded the use of low power verification capabilities in TSMC's Reference Flow 11 to meet complex IC low power functional verification requirements. The Mentor low power verification tool suite includes the Questa functional verification platform, the 0-In CDC (Clock Domain Crossing) and the 0-In Formal tools and the FormalPro equivalence checking tool.
Reference Flow 11.0, focuses on Electronic System Level (ESL) design, SoC Interconnect Fabric, and two dimensional and three dimensional integrated circuits (2-D/3-D ICs) using through silicon via (TSV) technology.
In June 2010, Mentor said it had further expanded the range of technologies included in TSMC Reference Flow 11.0.
The expanded Mentor track then provided a complete front-to-back solution with new support for the Vista platform and the Catapult C synthesis tool, expanded low power and 28nm routing features in the Olympus-SoC place and route system, and the Calibre InRoute solution, which provides Calibre signoff analysis and automated repair integrated in the Olympus-SoC physical design system.
In a statement, Mentor indicated that it intends to extend its collaboration with TSMC on future reference flow programs.
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