ASIC provider HiSilicon Technologies Co., Ltd. has deployed Synopsys' IC Compiler, a component of the company's Galaxy Implementation Platform, in its production design flow and claimed it has reduced stand-by power consumption by up to 40 percent.
HiSilicon specified that it has used Synopsys' IC Compiler in its production design flow for ICs targeting green networking applications.
IC Compiler’s new final-stage leakage recovery capability delivered 40 to 50 percent standby power savings while preserving timing on blocks in HiSilicon's recently taped out designs, the company claimed. It has since deployed final-stage leakage recovery in its production tape-out flow.
IC Compiler’s latest release provides a final-stage leakage recovery capability architected to manage a multitude of these leakage variants in order to reduce stand-by power consumption while preserving timing. HiSilicon said it initially exercised this capability on a few trial blocks and then on several blocks of a live tape out and succeeded in substantially lowering their power consumption.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.