Carbon Design Systems and MIPS Technologies have announced that they are collaborating to create and distribute virtual platform models of MIPS processor IP (intellectual property) cores. By creating the processor models from the production RTL (register transfer level) code for each MIPS core, Carbon is promising 100% cycle accuracy. MIPS will integrate the models and virtual platforms with their Navigator ICS (Integrated Component Suite), and the open-source GDB source-level debugger, to enable designers to perform interactive debug and analysis.
You can configure and generate the MIPS models at Carbon's IP Exchange web portal, and use them in Carbon's SoCDesigner Plus virtual platform or in a SystemC or RTL simulation environment. Carbon and MIPS are delivering models for the MIPS32 M14K and M14Kc cores now, and are planning to release additional processors models on a regular basis.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.