MathWorks announced that Simulink Design Verifier now includes Polyspace analysis technology for automated error detection in Simulink models. Simulink Design Verifier 2.0 integrates Polyspace error detection with existing property proving and test generation capabilities to help reduce the time required to find and fix the root cause of design errors, decreasing the overall cost of verification and validation.
Engineers across the aerospace, automotive, medical, and industrial automation and machinery industries can now apply Model-Based Design with formal analysis methods provided by Simulink Design Verifier 2.0 to identify design errors in Simulink and Stateflow models without extensive testing or simulation.
Key product features include:
. Detection of dead logic, integer and fixed-point overflows, division by zero, and assertion violation
. Blocks and functions for modeling functional and safety requirements
. Test vector generation from functional requirements and model coverage objectives
. Property proving, with generation of violation examples for analysis and debugging
. Fixed-point and floating-point model support
Simulink Design Verifier is available immediately. U.S. list prices start at $8000.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.