MultiPhy Ltd. is getting ready to sample next quarter the MP1100Q, claiming it as the first 100G PHY IC designed to meet the low-cost and low-power needs of the growing 100G metro transport market.
The MP1100Q is a quad 25Gb/s to 28Gb/s CMOS demux receiver. It employs advanced DSP-based receiver technology using Maximum Likelihood Sequence Estimation (MLSE) algorithms, which improves overall performance by overcoming fiber impairments, according to the company. The DSP-based MP11000Q integrates an analog-to-digital converter, high-speed CDR and DQPSK decoders.
Four inputs at 25Gb/s to 28.3Gb/s
MLSE/DSP-based high-performance algorithm
Integrated high-speed CDR
Integrated DQPSK decoders
Compliant with IEEE802.3ba, OTU4, and ITU-T G.709
Interfaces compliant with CAUI/MLD and OTL4.10 standards
Low power dissipation
On-chip, flexible PRBS error checker and pattern generator
Loss of Signal (LOS) and Loss of Lock (LOL) interfaces
SPI management interface for enhanced control and monitoring capabilities
Can be used in CFP optical module designs
Supply voltage: 1V cores, 1.5V analog I/Os, 3.3V digital I/Os
Temperature sense output voltage FCBGA Pb-free / RoHS package
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