Altera Corporation has launched what they claim is the industry's first Serial RapidIO Gen2 FPGA-based solution, enabling improved bandwidth and link flexibility for next-generation 3G and 4G wireless base station deployments. Altera says it has successfully interoperated its RapidIO MegaCore Function IP core implemented in a Stratix IV GX FPGA with a Serial RapidIO Gen 2 switch from Integrated Device Technology (IDT). The new Serial RapidIO Gen2 solution provides a 20-Gbaud packet-based interconnect for linking radio cards, host processors and digital signal processors used in high-performance communications systems.
Altera's Serial RapidIO Gen2 IP core interoperates with IDT's 80HCPS1848 switch in x1 and x4 configurations from 5 Gbaud up to 20 Gbaud. IDT is the only vendor to offer a Serial RapidIO Gen2 switch.
Altera's Serial RapidIO MegaCore Function is available now for download as part of Altera's design suite, and is supported within Altera's Quartus II software version 11.0. The IP core is available as encrypted IP or as source code for complete user control. For access to the interoperability test report, contact email@example.com.
Toni McConnel covers new products in the embedded systems industry and is a partner in the technical writing team TechRite Associates. She can be reached at Toni@TechRite-Associates.com.