The other day I talked to the folks at Apache about a new product they are releasing today called the RTL Power Model (RPM – got to love multi-layered acronyms). Now on the surface this doesn’t sound particularly new or exciting because people have been doing power optimization at the RTL level for quite some time now. At the same time I know, as do we all these days, that power and battery life has gone from a secondary design consideration to a primary one. I don’t want to be recharging my devices every five minutes, and so I listened to try and find out what was new.
In their words RPM bridges the power gap from register-transfer-language (RTL) design to physical implementation. The new technology accurately predicts integrated circuit (IC) power behavior at the RTL level with consideration for how the design is physically implemented. As a result, the technology helps to enable chip power delivery network (PDN) and IC package design decisions early in the design process, as well as to ensure chip power integrity sign-off for sub-28nm ICs.
I was intrigued about power integrity. We have heard a lot in the past about signal integrity, but how was this different. Well for starters when there are multiple power domains or clock domains, interesting things can happen when you turn them on and off. Current spikes and stuff like that. But these things don’t just affect the chip, they affect the analog portions of the design, the packaging and the board. So part of this product offering is bringing all of their point tool solutions together into a power flow with information being passed between them to ensure that nothing gets lost in the cracks.
By moving the start of the process up to the RTL level, much longer or more in-depth simulations can be run to identify where the problems may be hiding and then more detailed analysis can be performed in those regions. They say that they can accurately identify a few cycles representing the transient and peak power characteristics from millions of vectors within hours. This gives them a 10-30X speed-up over doing the same analysis at the gate level. This of course relies on a fast and predictable estimator and that is a core part of this announcement. In their words “As a new offering to Apache's PowerArtist™-XP software, RPM's core technologies include PowerArtist Calibrator and Estimator (PACE™) for accurate power estimation at the RTL level prior to availability of physical layout as well as Fast Frame-Selector for critical power-aware cycle selection.”
They are using data-mining and pre-characterization techniques to create power and capacitance models, rather than traditional wire load models intended for timing closure. By considering characteristics for various circuit types, such as combinational logic and sequential elements, PACE is designed to delivers RTL power within 15 percent of gate-level power results
So there you have it.
If you want more information, you can find it on their website
– keeping you covered
If you found this article to be of interest, visit EDA Designline
where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here
to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).