Cadence has long been the underdog in the RTL synthesis market but with their latest release of the Encounter® RTL-to-GDSII flow they believe they have what it takes to gain market share, although their lawyers will not permit them to say that. The main reason for this is the connection they have established between physical synthesis and layout optimization that brings about better designs and faster design closure.
Before we got started on their presentation, I asked Rahul Deokar, the Product Marketing Manager for Encounter, about the adoption of various technology nodes. He told me that the mainstream is around 65 and 40nm today. 28nm is the place for the leading edge customers who want to separate themselves from the pack and 20nm is still early and Cadence is working with the IP vendors and fabs to make sure test silicon is working properly and that the flows are robust enough for their customers when they need it.
They are basing their optimism on three factors – performance, size and advanced node features. Designs today contain multiple embedded ARM processor approaching 1GHz or more and customers need lots of help with these designs. In the performance part of the equation we have gone from being concerned about area and speed to PPA – Power, Performance and Area, and Rahul said that this is indeed the order of importance for many designs.
Much of their performance gains come from bringing the physical synthesis and optimization together with an added dose of some technology they acquired from Azuro last year that gives them a significant boost in the clock optimization. Cadence calls this CCOpt (Clock Concurrent Optimization). Rahul estimated that clocks consume 20 to 25% of a chips power, and they are seeing a 40% reduction in clock power in one design example. These gains are going to mean improvements in all technology nodes, although the gains increase with the latest nodes and larger designs.
Double patterning is specific to 20nm and not likely to be used for larger nodes. It causes an explosion in the number of DRC and DPT rules which have large run times associated with them. The Cadence approach does not rely on a post-processing strategy, but instead works in a correct-by-construction approach.
As a demonstration of their leadership Cadence can still point to the TSMC test chip for a 20nm ARM Cortex-A15 processor announced in October last year – a feat that has not yet been matched by any other company.
Brian Bailey – keeping you covered
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