Self-calibrating logic IP for double data rate (DDR) memory subsystems now solves dynamic variation problems during system operation. Developed by Uniquify, dynamic self-calibrating logic (DSCL) provides real-time calibration to accommodate dynamic variations in the system operating environment. It allows the memory subsystem timing calibration to be applied during system operation, which is critical to enhancing system yield and maintaining DDR memory system performance as temperature and supply voltages fluctuate during system operation. The technology is included as part of Uniquify’s DDR PHY/Controller subsystem IP.
“Even small changes in system operating parameters over time can degrade memory performance and cause failures,” notes Uniquify founder and CEO Josh Lee. “This will become an even greater issue as the industry adopts next-generation DDR4 memories with stringent timing requirements."
Today’s deep sub-micron SoC designs integrate DDR memory subsystems that operate at multi-gigahertz (GHz) clock rates, resulting in read-write timing margins measured in picoseconds. Designing the DDR memory subsystem to accommodate variations in system-level timing parameters during read and write cycles is challenging. Satisfying these critical timing requirements can require exhaustive rounds of incremental system-level parameter tuning, yet the resulting silicon often fails to deliver optimal system yield in volume production.
Uniquify's initial SCL technology solves this problem by performing an automatic self-calibration at system power-up for optimal DDR interface timing. DDR memory subsystems implemented with SCL exhibit higher yield due to their ability to automatically adapt critical timing characteristics for a wide range of system-level design choices and for variations in both the SoC and DDR memory processes.
The new DSCL technology builds on SCL by extending the precise timing calibration to execute dynamically during system operation, not just at system power on. During system operation, temperature and supply voltages vary over time, degrading DDR memory performance and, if severe enough, can cause intermittent memory subsystem failure.
DSCL automatically re-calibrates the critical DDR memory interface timing at user-specified intervals during system operation. It is typically set to operate during periods of lower activity for the smallest impact on system throughput. The DSCL calibration is fast and the hardware required to support the addition of DSCL is minimal.
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