The more help you can provide, the faster a company is able to get a quality product out of the door, with less risk involved. That is the objective of the Processor Optimization Packs (POP)s from ARM. Today they are launching a bunch of new ones targeting the TSMC 40nm and 28nm processes including Cortex-A5, Cortex-A7, Cortex-A9 and Cortex-A15 processor cores. POPs enable quickly timing closure for single-, dual- and quad-core implementations across a broad envelope of power, performance and area optimization points. The summary of existing and new POPs is shown below.
A Processor Optimization Pack solution is composed of three elements:
- it contains ARM Artisan Physical IP logic libraries and memory instances that are tuned for a given ARM core and process technology.
- it includes a comprehensive benchmarking report to document the exact conditions and results ARM achieved for the core implementation.
- it includes a POP Implementation Guide that details the methodology used to achieve the result, to enable the end customer to achieve the same implementation quickly and at low risk.
Given the focus on power at the moment, I asked them about their approach to power. I was told that their primary focus is on performance while being careful about power. They do use multiple thresholds in the library and they ensure the cores work with DVFS techniques. They also provide guidance for clock and power gating. On their benchmark sheet for the Cortex-A9 MPCore +L2C-310+PTM they show the following power figures which are meant to be worst case.
The following chart gives a feel for the range of solutions possible, even though the axes are unscaled.Brian Bailey
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