Solido Design Automation has released its High-Sigma Monte Carlo
(HSMC) meta-simulator solution, aimed at providing accurate, scalable
and verifiable analysis and design solutions for memory chips.
The tool is claimed to be 100x+ faster than Monte Carlo analysis. Memory IP is an integral part of SoC design, and requires low power, minimum cost and die area, and maximum performance at high yield. As a result, memory designers are early adopters of state-of-the-art foundry processes (28 nm and below). The increased variability associated with these new processes leads to increased risks in yield while meeting aggressive power, performance and area goals.
Many memory elements, such as bit cells and sense amps, are replicated in large arrays so that producing a single working product requires that the millions of repeated cells all work correctly, without failure. This makes high yield design a requirement; by definition, 5 sigma has only one failure in two million, and 6 sigma has only one failure in a billion. The number of simulations required to validate high yield using traditional methods is simply infeasible, even with today's fastest simulators, and even while utilizing massive compute clusters and cloud computing.
There is a continuing progression of electronic design automation tools to manage increased complexity through greater abstraction and partitioning methods. Meta-simulators are part of this trend. A meta-simulator feels like using a single simulator to the designer, yet drives hundreds or thousands of simulations in parallel from traditional simulation engines. Meta-simulators offer a “meta-level” analysis that may use a large number of simulations, while keeping the user input to not much more than a netlist. The output is simple, numerical, and well-defined, just like the result of a simulation.
Meta-simulation has historically been limited to simplistic methods, such as running corners or running Monte Carlo. Today, meta-simulation techniques can be much more powerful, addressing designer challenges and speeding up different analyses types in precisely-targeted ways. For example, rather than running 100 or 10,000 PVT corners just to search for the worst cases, a “Fast PVT” meta-simulator would analyze all the PVT corners and intelligently simulate only the small subset requires to identify the worst-case corners with confidence.
Meta-simulation goes beyond distributed processing; it also adds efficiency to high-value analysis capabilities such as: fast PVT analysis; fast extraction of statistical corners; and fast sensitivity analysis. An ideal meta-simulator for memory design measures yield-performance tradeoffs out to 5 and 6 sigma, with the same accuracy as millions or billions of Monte Carlo simulations, but with 100x+ fewer simulations.
Solido High-Sigma Monte Carlo meta-simulator provides rapid analysis of yield-performance tradeoffs for memory design. It achieves high-sigma memory verification in thousands rather than millions or billions of simulations. It analyzes the billions of Monte Carlo samples, and then focuses its SPICE simulation resources to find rare failures or validating the target yield. The tool runs fast enough to facilitate both iterative design and verification within production timelines, enabling yield-performance tradeoffs. It interfaces to all the leading SPICE simulators used by memory designers.
Visit Solido Design Automation at www.solidodesign.com.
This article appears courtesy of EE Times Europe.
Did you find this article of interest? Then visit the Memory DesignLine
where we update daily with design, technology, product, and news
articles tailored to fit your world. Too busy to go every day? Sign up
for our newsletter to get the week's best items delivered to your inbox.
Just click here
and choose the "Manage Newsletters" tab.