Today, Xilinx is launching their Vivado Design Suite, heralding the second generation of tools for programmable systems. Up until this point, it had been possible for FPGA vendors to get away with techniques that were easier to implement, but these had been progressively struggling to meet the demands of the newer high capacity devices. When you adds processors to the mix of programmability and what may be possible in the near future with 3D stacked silicon, it became clear to Xilinx that they had to do a rethink of their entire software flow and to start thinking about the development of a design for an FPGA in a similar manner to ASIC development. That includes the latest types of algorithms for placement and routing as well and concentration of the productivity of the designers.
If EDA vendors though it was difficult to play in an FPGA flow in the past because of the price points, they may struggle even more now – even though Vivado is a lot more open than their previous systems. This may present an opportunity for startups who consider a different business model from the get-go.
Anchoring the new system is an integrated development environment (IDE) that operates on top of a unified database supporting all aspects of the flow include HDL code development, simulation and debug, IP authoring, importing and selection. All operations can either be done textually (Tcl) or graphically and you can switch between the two environments at any point in a session.
Vivado has been in development for four years with over 500 person years invested in it. While today is the official launch date, it is already in the hands of over 100 customers, including the large EDA companies for integration purposes. This is just the beginning. Not all of their existing software and flows have been integrated into the new environment yet, and aspects such as the SW development and integration are not expected before year end.
Two of the most significant changes that users will see are the new place and route engine. This will enable designs that could not be successfully routed in the past to be routed – often in a much smaller area, in a much more predictable manner. Xilinx also believes that it will achieve much better solutions that come close to finding the most optimal placement and routing. The second aspect is the inclusion of high-level synthesis that they acquired from AutoESL a while back. What may make many EDA companies feel sick is that Xilinx will be offering this for about $2000, a couple of orders of magnitude lower than existing sticker prices.
I will be writing more about specific parts of this new software flow in the near future.
Brian Bailey – keeping you covered
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