Micron Technology has begun sampling its first DDR4 DRAM module, with plans to begin volume product in Q4 2012. Codeveloped by Nanya and based on Micron's 30-nm technology, the 4-Gb DDR4 x8 part is the first piece of a portfolio that eventually will include RDIMMs, LRDIMMs, 3DS, SODIMMs, and UDIMMs (standard and ECC). Components in x8, x16, and x32 also will be available, featuring initial speeds up to 2400 megatransfers per second (MT/s) and then increasing to the JEDEC-defined 3200 MT/s.
"With the JEDEC definition for DDR4 very near finalization, we've put significant effort into ensuring that our first DDR4 product is as JEDEC-compatible as it can be at this final stage of its development," said Brian Shirley, vice president for Micron's DRAM Solutions Group. "We've provided samples to key partners in the market place with confidence that the die we give them now is the same die we will take into mass production."
The company expects the enterprise micro-server, ultrathin, and tablet markets to adopt the technology. For more information, visit www.micron.com.
DDR4 will eventually license NLST HyperCloud IP.
LRDIMMs are already at end-of-life - as they have adopted a bad implementation of the NLST IP.
DDR4 is more closely copying it.
LRDIMMs are currently only made by Inphi (others have backed off - IDTI and Texas Instruments).
However Inphi has been aggressive in copying NLST IP - but recently their reexamination of NLST patents '537 and '274 were re-validated by USPTO with ALL claims intact. This is going to bode badly for NLST vs. Inphi.
LRDIMMs will either be recalled, or negotiate a license from NLST.
DDR4 should license NLST IP before finalization as well.
Currently NLST HyperCloud is selling through IBM (as HCDIMM) and HP (as HP Smart Memory HyperCloud). It is the only memory capable of 1333MHz at 3 DPC on HP servers.
Inphi-based LRDIMMs have latency issues (because of their use of asymmetrical lines) - and they are unable to deliver 1333MHz at DPC (but 1066MHz).
How about covering NLST IP for a change - as it will be adopted by DDR4.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.