For a long time, it has been said that verification gets no respect. This is not only true for the engineers that perform this essential task, but also for the research community Ė that is only interested in formal verification, and for tool development because it never looks as if progress is really getting made. My theory about why universities do not tackle verification issues is because it is too large a problem for them to deal with.
About a year ago, Cadence announced a four pronged attack on verification, ranging from their virtual prototype, through the more traditional simulation platforms and then on to accelerations and prototyping.
Today Cadence is updating a few of those elements in ways that donít sound impressive, but are vital to progress being made in getting designs out the door faster and less risk of latent bugs. To that end, Cadence is now offering, as part of the System Development Suite, a single heterogeneous environment for system-level verification based on the Incisive and Palladium XP platforms, which enables designers to leverage both the high speed and real-world interfaces of traditional in-circuit emulation environments combined with the advanced analysis capabilities available in RTL simulation. Design teams are no longer forced to create and maintain both environments, spend unnecessary time and effort to reproduce bugs, or remodel all system components targeted for one environment - tasks which are not time effective and make sub-optimal use of the existing IP assets.
To go along with that, Cadence is also expanding their library of Universal Verification Model (UVM)-compatible Accelerated VIP models that are compatible across the range of simulation to acceleration, in-circuit acceleration, and in-circuit emulation. The Cadence accelerated VIP catalog now includes ARM's AMBA AXI 3/4 and ACE, PCI Express 2.0/3.0, USB 3.0, 10Gb Ethernet, SATA 3, and HDMI 1.4.
Brian Bailey Ė keeping you covered
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