A highly configurable controller IP core designed for the hybrid memory cube (HMC) allows vendors to integrate HMC technology into their next-generation systems. Targeting high-performance computing, networking, and test and measurement applications, the HMC controller IP core from Open-Silicon builds on high-bandwidth serial protocols derived from the company’s Interlaken controller IP core.
Supporting up to 240 GBps, the high-performance HMC controller IP also offers ultra-low latency and a flexible user interface. As a fully synchronous, soft-core implementation suitable for ASICs and FPGAs, along with robust error detection and automatic retry, the core supports up to four HMC links managed by a single controller. Each link consists of 16 lanes of 10, 12.5 or 15 Gbps.
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