A family of DDR3L memory modules features an ultra-low profile for communications and networking applications. The Blade VLP modules from Virtium are available now in 4-GB and 8-GB densities in a wide range of ECC SODIMM, RDIMM, UDIMM, and Mini DIMM configurations. By reducing the height from the JEDEC-standard VLP of 18.75 mm to 17.78-mm profile, the modules present a good solution for telecom and networking applications in which it is difficult to accommodate the memory required for both an industry-standard DIMM or Mini DIMM socket plus a standard VLP at the 18.75 mm height.
Virtium's low power DDR3L memory modules are designed to reduce the total power in systems that use multiple memory modules and those that must run at higher temperatures, which is a typical design challenge in a wide range of AdvancedTCA-based telecom and Ethernet blade switch networking applications. The reduced form factor not only solves space constraints allowing more air flow in the system, but also boosts system performance by incorporating low power DRAM that reduces thermal dissipation by up to 10°C on the DRAM surface. This is a particular design advantage as JEDEC specifies that systems running memory beyond 85°C must double the memory self-refresh rate.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.