Synopsys Inc. will update its DesignWare DDR interface IP portfolio with support for DDR4-based SDRAMs. With support for DDR4, DDR3 and LPDDR2/3 in a single core, the DesignWare DDR IP portfolio enables interfacing with both high-performance and low-power SDRAMs in one SoC, as required in applications processors for smartphones and tablets.
The IP solution includes the DDR4 multi-PHY and Enhanced Universal DDR Memory Controller (uMCTL2) that connect through a commonly used DFI 3.1 interface.
The DDR4 IP supports all the key DDR4 features planned for the upcoming JEDEC standard. It claims to offer 13 percent increase in raw bandwidth and up to 50 less overall latency compared with the previous version. It is also said to include intelligent system monitoring and control to power down elements of the IP as determined by the system's traffic patterns, resulting in lower power use.
Also, real-time scheduling features in Synopsys' unique CAM-based DDR controller can optimize the scheduling of data read/write traffic from multiple hosts, maximizing performance and minimizing latency.
The DesignWare DDR4 multi-PHY and Enhanced Universal DDR Memory Controller (uMCTL2) with support for DDR4 is expected to be available in Q4 12.
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