A new LPDDR3 memory architecture, which includes a controller and DRAM interface, supports data rates between 1600 Mb/s and 3200 Mb/s. Aimed at the mobile industry, the Rambus Inc. R+ LPDDR3 can reduce active memory system power consumption by up to 25% and active DRAM power demand by up to 30%. The performance is driven by a low-swing implementation of the Rambus near-ground signaling technology. Essentially, this single-ended, ground-terminated signaling technology allows devices to achieve higher data rates with significantly reduced I/O power to improve functionality for streaming HD video, gaming, and data-intensive apps on mobile devices, says Rambus.
The R+ LPDDR3 architecture is built from ground up to be backward compatible with LPDDR3 supporting same protocol, power states, and existing package definitions and system environments. The product was designed using the Globalfoundries 28-nm SLP process technology.
Additional features include:
Multi-modal support for LPDDR2, LPDDR3, and R+ LPDDR3
DFI 3.1 and JEDEC LPDDR3 standards compliant
Supports package-on-package and discrete packaging types
LabStation software environment for bring-up, characterization, and validation in end-user application
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.