Tensilica has introduced IVP, an imaging and video dataplane processor (DPU) that is intended for the complex image/video signal processing functions in mobile handsets, tablets, digital televisions (DTV), automotive, video games and computer vision based applications.
The IVP DPU is a much-needed breakthrough product in terms of energy efficiency and performance in current products and to enable applications never before possible in a programmable device. IVP is supported by a network of third-party application developers who are actively porting leading-edge image applications to the IVP platform, including innovative multi-frame image capture and video pre- and post-processing algorithms, as well as established yet evolving technologies such as video stabilization, high dynamic range (HDR) image, video HDR, object and face recognition and tracking, low-light image enhancement, digital zoom and gesture recognition.
The IVP DSP has a unique instruction set tuned for imaging and video pixel processing that gives it an instruction throughput of over 16x the number of 16-bit pixel operations compared to that of the typical host CPU with single-issue vector instructions. In addition to its raw instruction throughput advantage to host CPUs, the imaging specific compound instructions supported by IVP give it a higher peak performance of 10 to 20x and much higher energy efficiency. IVP's rich instruction set has more than 300 imaging, video and vision-oriented vector operations, each of which applies to 32 or more 16-bit pixels per cycle.
Tensilica's IVP is based on a 4-way VLIW (very long instruction word) architecture that delivers high parallelism intermixed with code-compact instructions, with a 32-way vector SIMD (single instruction, multiple data) dataset. The architecture includes an integrated DMA (direct memory access) transfer engine with up to 10 GBytes/second of throughput and local memory throughput of 1024 bits per cycle (sixty-four 16-bit pixels/cycle) to keep up with the rapid pace of resolution and frame rate requirements. The IVP also features many imaging-specific operations to accelerate 8-, 16- and 32-bit pixel data types and video operation patterns.
The IVP is extremely power efficient. As an example, for IVP implemented in an automatic synthesis, place-and-route flow in 28nm HPM process, regular Vt, a 32-bit integral image computation on 16-bit pixel data at 1080p30 consumes 10.8 mW. The integral image function is commonly used in applications such as face and object detection and gesture recognition.
IVP's high performance is demonstrated by complex algorithm kernels such as motion search and normalized cross-correlation, commonly used in high-precision block and feature matching and optical flow. For a smart motion search on 16-bit data over a 1920x1080 frame with 256x16 pixel search range and 9x3 pixel block size, IVP can achieve a rate of 142 sums of absolute differences per cycle. In addition, a normalized cross-correlation function on 16-bit pixel data with 32-bit accuracy achieves 1 million 8x8 blocks per second. Many companies have proprietary imaging and computer vision algorithms which can be implemented on the IVP, as it employs the C programming model common among all Tensilica DPUs. Tensilica has also created a partner network to enable availability of pre-ported, efficient third-party imaging software. Initial partner companies porting advanced imaging suites to the IVP DPU include Almalence, Irida Labs, Dream Chip Technologies and Morpho, Inc.
Early-access lead customers took delivery of IVP last year, and the IVP DPU is available for broad licensing now.