A pair of new FRAM products featuring an SPI serial interface guarantees 1013 read/write cycles. Geared toward applications such as industrial machinery and medical devices, the 1-Mb and 2-Mb FRAM offerings from Fujitsu Semiconductor consume 92% less power during writing compared to identical-density EEPROM. The MB85RS1MT and MB85RS2MT incorporate all the technology required for system memory components into a single chip, lowering power consumption. Additionally, the memory itself fits into a smaller package size, reducing the mounted area required for memory components by more than 90%.
The 10-trillion read/write cycle count marks a 10-fold improvement over Fujitsu’s existing FRAM. The upgrade minimizes the risk of data loss from sudden voltage drops or power outages. Offering 10 years of data retention, the devices are nonvolatile, eliminating the cost and space required for a backup battery. Operating power supply voltage for both versions runs from 1.8 V to 3.6 V.
The new products will be available in sample quantities starting in late March. Visit Fujitsu to view the data sheets.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.