Symtavision has added Ethernet timing analysis to its SymTA/S tool for
the design and verification of embedded real-time systems. The new
Ethernet timing analysis targets the automotive market and integrates
with the existing in-vehicle network timing analyses for CAN and FlexRay
as well as with scheduling analysis for AUTOSAR-based ECUs.
SymTA/S Ethernet analysis capability focuses on timing design and
verification for both standard IP Ethernet (Layer 3) and Audio Video
Bridging (AVB). The SymTA/S Ethernet model covers entire Ethernet
networks including ECUs, switches, ports, messages, PDUs and links which
can be directly combined with other bus systems like FlexRay and CAN,
in addition to white box or black box gateways. Furthermore, the model
supports the co-existence of internal ECU scheduling and Ethernet
communication, including any triggering and synchronization
requirements. The model can also be scripted for easy tool chain
integration and model transformation of existing Ethernet communication
SymTA/S Ethernet analysis capability covers different communication
priorities, MTU sizes, scheduling strategies, and transmission rates as
individual rates per port as well as automatic end-to-end hop
resolution, static routes, traffic classes, and single cast, broadcast and multicast communication, including multiple hops over switches for star or other topologies.
metrics are provided for load and load-over-time of each port or on a
switch as well as buffer fill levels as absolute or as over-time values
for each port and switch. In addition, response times are provided for
each Ethernet message and data communication paths can be observed for
different end-to-end scenarios. Each result can be validated against
constraints and the timing can be debugged individually through Gantt chart visualization, including point-of-interest functions such as deadline violations.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.