Cadence Design Systems has launched a new static timing analysis
and closure tool designed to run on passively parallel hardware and
enable System-on-Chip (SoC) developers to speed timing closure and move
chip designs to fabrication quickly.
The Tempus Timing Signoff Solution represents a new approach
to timing signoff tools that enables customers to shrink timing signoff
closure and analysis for faster tapeout while producing designs with
less pessimism, area and power consumption.
“Today, the time spent in timing closure and signoff is approaching 40
percent of the overall design implementation flow. Traditional signoff
flows have failed to keep pace with the increasing demands of achieving
timing closure on complex designs,” said Anirudh Devgan, corporate vice
president for Silicon Signoff and Verification for the Silicon
Realization Group at Cadence. “The Tempus Timing Signoff Solution
represents a significant advancement in timing signoff tool innovation
and performance, leveraging multi-processing and ECO features to achieve
signoff faster than with traditional flows.”
Tempus is the the first massively distributed parallel timing engine on
the market, which can scale to use up to hundreds of CPUs. The parallel
architecture enables the tools to analyze designs in the hundreds of
millions of instances without compromising accuracy.
A new path-based analysis engine leverages multi-core processing to
reduce pessimism. With its performance advantage, the Tempus Timing
Signoff Solution enables broader use of path-based analysis. Multi-mode,
multi-corner (MMMC) analysis and physically-aware timing closure
leverages multi-threaded and distributed timing analysis.
The Tempus Timing Signoff Solution advanced capabilities can handle
designs containing hundreds of millions of cell instances without
compromising accuracy. Initial engagements with customers have shown the
tool can achieve timing closure in days on a design that would have
taken several weeks with traditional flows.
“We are pleased to see new capabilities in the area of static timing
analysis (STA) from Cadence,” said Sanjive Agarwala, director of
processor development at Texas Instruments. “As we move to more
advanced process nodes, timing closure becomes more difficult. It’s
great to see Cadence taking on this challenge by offering new technology
designed to tackle tough design closure issues.”
This article originally appeared on EE Times Europe.