EnSilica has established a special licensing deal to encourage existing 8051 licensees to switch their next ASIC design start to an eSi-1600 16-bit soft processor core.
For all enquiries received before January 31, 2011 and subject to terms and conditions, EnSilica is offering to match their 8051 license fee.
"We have declared ‘open season’ on the 8051," said David Wheeler, Technical Director of EnSilica. "Where a small and relatively inexpensive processor is required, the 8051 is probably still the most popular choice. However, the eSi-1600 offers considerable additional benefits over even the most optimized 8051, particularly in terms of low power and silicon area which are so important in today’s competitive marketplace. What’s more, the eSi-1600 soft processor core delivers these additional benefits at a very competitive price."
EnSilica’s eSi-1600 provides 65 times the performance of the original 8051 (Dhrystone DMIPs/MHz) and more than 5 times the performance of the fastest, enhanced 8051. This allows the clock to be disabled for 80 percent of the time relative to an 8051, delivering power savings.
Comparing the Dhrystone kernel size, the eSi-1600’s mixed 16/32-bit instruction set occupies only 60% of the code size required by the 8051, providing substantial savings in silicon area and power associated with the program memory. The eSi-1600’s core size is 8.5k gates.
Also it will be good to learn from the experience of anyone who might have already used any of the soft controller cores from EnSilica. I would appreciate if any of the users shares his or her views on this product if he or she experienced using IP core from EnSilica in ASIC/FPGA design.
The product looks interesting specially when the 16-bit controller core consumes only 8.5K gates! As I have a feeling after visiting EnSilica's website, that their customer base is mostly in Europe (especially in UK), I am interested to know if their service is available for the customers outside Europe as well.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.