Using what they describe as "a breakthrough in automated FPGA-to-ASIC conversion," fabless semiconductor company KaiSemi say that they can provide customers with a seamless, full turnkey FPGA-to-ASIC solution and sell fully compatible replacement chips at a fraction of the price.
I had a long chat with KaiSemi CEO Gal Gilat earlier this week, and I must say that I was very impressed with what he told me. Today's announcement is focused on introducing KaiSemi to the world at large (they are already well-known in Israel) – in future articles we will consider the KaiSemi flow in much more detail.
For the moment, we need only note that KaiSemi's proven process uses a unique in-house tool, which performs an automated conversion directly from the original FPGA netlist into a functionally-identical ASIC gate-level netlist. This is a key point – they don’t touch the RTL for the FPGA – instead they take the final ("golden") fully-functional FPGA netlist and work from that. In addition to the programmable logic itself, conversion process also includes all hard IP blocks in the FPGA, such as DSP cores, RAM blocks, PLLs, Clock Managers, and external interfaces (DDR, PCIe, etc.).
Backed by a tier-one fab vendor, KaiSemi's automated conversion utilizes a database of multiple proven standard-cell fab process libraries and standard cores. The wide range of libraries enables the conversion of any type and size of FPGA from any FPGA vendor while providing deep cost optimization during the automated conversion. The resulting ASICs – which are pin-compatible, timing-compatible, and functionally identical to the original FPGAs – consume significantly less power and cost up to 70% less than their FPGA counterparts.
KaiSemi's automated conversion and flow eliminates the need for customer involvement and resources, NRE costs, long lead times, and the risks that are part of traditional FPGA-to-ASIC conversion flows. KaiSemi manages the whole FPGA-to-ASIC process for the customer, from the purchase order through conversion, the ASIC flow, manufacturing, all the way through to the shipment of the ASIC chips. This seamless conversion process – combined with the Zero NRE model – lets the customer order an ASIC chip as if it were an off-the-shelf second-source replacement chip with a relatively short lead-time.
KaiSemi is set to exhibit in Electronica 2010 trade show in Munich, Germany, from November 9th to November 12th in Hall A5, booth #166.
For more information, visit the KaiSemi website (www.kaisemi.com
) or email the head of sales and marketing Avi Pinkas (firstname.lastname@example.org