The folks at GateRocket – specialists in verification and debug solutions for advanced FPGAs – have just announced a collaborative solution with Mentor Graphics that streamlines the verification-through-synthesis flow for advanced FPGA design.
This solution is especially well-tuned for developers of FPGAs targeting safety-critical applications in military and aerospace markets. It combines the performance and efficiency of GateRocket’s tool set for FPGA debug and verification with Mentor’s Precision Synthesis solution, a high-performance FPGA tool suite that is also claimed to be the industry’s first rad-tolerant synthesis-based solution.
In addition to new levels of performance and efficiency throughout the FPGA design process for any type of application, the integration allows designers to more efficiently verify and debug important high-reliability features such as synthesis-based triple modular redundancy (TMR) and compliance with safety-critical standards such as DO-254.
The collaboration expands GateRocket’s support for industry-leading FPGA synthesis tools, enabling a more efficient design flow for users of Mentor’s Precision Synthesis products. The GateRocket offering, which includes the RocketDrive verification platform and RocketVision debug tool, significantly reduces excessive iterations through synthesis and place-and-route caused by unforeseen design errors introduced by IP blocks and downstream design flows.
It also allows the verification of the FPGA to be done by using the targeted FPGA itself, in the RocketDrive system, which provides unmatched accuracy as well as enhanced verification performance. The resulting methodology cuts the number of synthesis-to-place-and-route iterations typically required in the development of complex FPGAs, a growing bottleneck as FPGAs increase in size and complexity.
An engineer working with Questa and debugging an FPGA design with a RocketDrive.
Support for Mentor’s Precision Synthesis complements GateRocket’s collaboration with Mentor’s verification solutions – ModelSim and Questa – to provide a unique flow that integrates simulation, synthesis, and hardware test.
High-reliability and safety-critical support
The combination of the Mentor and GateRocket tools will provide a more efficient approach to ensure circuits implementing high-reliability and safety-critical features are working properly and can be mapped error-free to the target FPGA device.
Mentor’s Precision Rad-Tolerant FPGA synthesis tool has been developed for aerospace and high- reliability applications to reduce the risk of functionality problems caused by single event upset (SEU) and single event transient (SET) disruptions. It automates a variety of radiation effects mitigation schemes, such as multi-vendor, multi-mode TMR.
Other supported mitigation technologies include fault-tolerant finite state machines (FSMs) as well as state machines that detect and recover from SEUs for all FSM encoding schemes. These forms of safeguards meet the needs of a wide range of high-reliability applications. The Precision Rad-Tolerant solution also delivers all of the unique synthesis-based capabilities of Precision RTL Plus, including low power synthesis and specialized features and flows for mil-aero and safety-critical applications.
The GateRocket "soft patch" feature in its RocketVision debug tool allows what-if analysis of potential SEU-causing errors. With the tool, designers can inject ‘soft upsets’ into the design under test and ensure that the hardware responds correctly. The solution is well-suited for product developers who must comply with DO-254, a standard mandated by the FAA and other aviation authorities to ensure the safety of in-flight hardware. DO-254 mandates that verification should be performed at all key stages of design – from conceptual analysis to in-system test. It is essential in a DO-254 program to ensure that the physical device behaves identically to the thoroughly verified model. The RocketDrive system enables thorough DO-254 compliant verification that is reusable for both verifying the model and testing the actual hardware. This allows a user to quickly prove that the FPGA behaves the same as the model, and ensure that a thoroughly verified FPGA is passed along to the in-target phase of test.
The benefits of the combined solution will be discussed during Mentor’s webinar on Safety Critical Design on September 21-22 (Click Here
for more details and to register).