Claiming a breakthrough in speed for the high-performance segment, Analog Devices today announced the AD9647 16-bit A/D converter operating at 250 MSPS (mega samples per second).
The device, intended to drive the company’s converter presence broader and deeper into military, industrial and wireless applications, is said to have a sampling rate that is25 percent faster than competitive devices. It uses 35 percent less power, at 1.32W total power dissipation including drivers, than competing devices, the company claimed.
1.8 V and 3.3 V supply operation
16-bit resolution with high signal bandwidths up to 300 MHz
On-chip IF (intermediate frequency) sampling circuit and buffered analog inputs
High dynamic range over broad signal bandwidth enables software-defined radios for use with multiple standards, such as LTE/W-CDMA, MC-GSM (class 1) and CDMA.
75.5 dBFS SNR to 170 MHz at 250 MSPS @ 2.5 V p-p FS
74 dBFS SNR to 170 MHz at 250 MSPS @ 2.0 V p-p FS
90 dBFS SFDR to 300 MHz at 250 MSPS (@ −1 dBFS)
at 2.5 V p-p FS
95 dBFS SFDR to 170 MHz at 250 MSPS (@ −1 dBFS)
at 2.0 V p-p FS
100 dBFS SFDR at 100 MHz at 160 MSPS (@ −1 dBFS)
60 fs rms Jitter
“This is a breakthrough device. It’s pushing the state of art,” Jon Hall, ADI’s strategic marketing and applications manager for high-speed converters, said in an interview.
The performance and power gains came thanks to a process shift rather than a process shrink.
The device is fabricated on .18 silicon germanium BiCMOS, where similar earlier devices were in CMOS.
The higher performance achievement enables ADI to push deeper into target applications. In wireless, for example, a higher sampling rate makes the devices suitable for multi-interface radio designs that may including for example, support for LTE, multi-carrier GSM and WiMax in a single system.
It also helps overcome the so-called near-far problem, in which a stronger signal that has captured a receiver makes it impossible to detect weaker signals. Better ADC resolution can resolve this problem by making it easier to detect weaker signals.
Availability: Sampling now; production volumes scheduled for November.
Pricing: $120 (250 MSPS); $100 (200 MSPS). Evaluation boards are available as well (see chart below).
The latency of the AD9467 is determined by the actual pipeline architecture. The AD9467 has multiple multi-bit stages followed by a digital block that aligns the raw bits and presents the sample to the output drivers. This all adds up to 16 clock cycles.