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eASIC Nextreme

10/5/2010 05:52 PM EDT
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Max The Magnificent
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re: eASIC Nextreme
Max The Magnificent   10/5/2010 6:07:03 PM
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As we plunge into lower and lower technology nodes, designing regular ASICs becomes harder and harder. The great thing about eASIC's single-via configuration technology is that the interconnect can be pre-characterized, so the delays are very deterministic; also eASIC have already handled the vast majority of signal integrity and similar problems. The result is fast turn around and relatively low NRE for devices that are much faster and consume much less power than regular FPGAs. However there is an overhead, so they don't really reach full ASIC capabilities. I'm guessing 75% of the performance of a regular ASIC and 130% the power consumption (at the same technology node). Does anyone have better figures?

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