It's always nice to hear good news. It seems that, using eASIC's NEW ASIC devices, the folks at On-Ramp Wireless, providers of low-power, wide area scalable wireless networking systems successfully rolled out their eNODE Wireless modules six months ahead of schedule
Just to remind ourselves, eASIC's Nextreme (90 nm) and Nextreme2 (45 nm) NEW ASICs are based on a configurable fabric that combines efficient Look-Up-Table (LUT)-based logic with single via-layer customized interconnect.
These devices offer a number of advantages for designers considering standard cell ASICs, FPGAs, and ASSPs, such as ASIC-like performance, power, and low unit-cost combined with an FPGA-like design flow and rapid delivery of devices.
The fast-turnaround for On-Ramp Wireless was facilitated by eASIC's NEW ASICs, which form a part of the eNODE baseband processing engine. eNODE wireless modules are used in wide area, low power and low data rate applications such as sensor monitoring, utility distribution automation, smart metering, and location tracking, to name some examples.
Built on On-Ramp's Ultra-Link Processing (ULP) technology, the eNode is the first wireless module to provide metro-scale wireless networking in unlicensed ISM-bands. ULP also enables the system to provide a significant increase in network capacity, which substantially lowers network infrastructure and cost.
eASIC's NEW ASICs provide designers with a unique platform for reducing the time (and development cost) of custom chip designs, compared to traditional cell-based ASICs. Designers are able to implement designs and receive fully tested chips back in a fraction of the time, thereby enabling early customer traction and market penetration.
In addition to enabling fast market access, eASIC's patented technology enables device manufacturing to commence ahead of design completion. Wafers can be staged and customized late in the manufacturing cycle for unique customer designs enabling OEMs to receive tested ASIC devices only six weeks after design tape-out.
"eASIC's devices provided us with an inexpensive vehicle to get to market and ramp up production quickly," commented Jonas Olsen, Vice President of Marketing at On-Ramp Wireless. "As we target many markets that are still emerging, development cost, development time, and flexibility to innovate and change quickly are critical."
As we plunge into lower and lower technology nodes, designing regular ASICs becomes harder and harder. The great thing about eASIC's single-via configuration technology is that the interconnect can be pre-characterized, so the delays are very deterministic; also eASIC have already handled the vast majority of signal integrity and similar problems. The result is fast turn around and relatively low NRE for devices that are much faster and consume much less power than regular FPGAs. However there is an overhead, so they don't really reach full ASIC capabilities. I'm guessing 75% of the performance of a regular ASIC and 130% the power consumption (at the same technology node). Does anyone have better figures?
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